This is just a very basic document. The following items automatically generate references in the References Appendix. [[!REX]] Yeah for memes [[MEMES]]. [[DOM4]], [[XML10]], [[\WHATEVER]]
Note that this example document turns on the addDefinitionMap flag in the
respecConfig. This inserts the Definition Map Appendix.
There are a number of areas that still need work. Some of them are visible in this document and some of them are background issues. The main html that users would write is pretty solid. Work areas include:
blah
blahblah
blahblah
Support has been added to automatically detect, format, and link terms and associated definitions.
Terms are defined using the <dfn class="xxx"> tag.
Term namespaces are independent for each class (e.g. it's OK to have
<dfn class="pin">foo</dfn> and
<dfn class="signal">foo</dfn>.
Valid class values are:
Term references use the <a> tag with no href attribute.This is a footnote.
The class is OPTIONAL and is only needed to resolve ambiguity (e.g.
<a class="pin">foo</a> vs <a class="signal">foo</a>).
When the contents of a term definition contains HTML tags (e.g. <sub>, <abbr>), this HTML is remembered
and is copied to the references.
This makes subscripts and abbreviations more convenient since
<a>D0active</a> could expand to
<a href="#state-D0-active" class="state">D0<sub>active</sub> D0activeThe
<a> references the text of the in <dfn> the <a> is the text after removing HTML tags.
The contents of the <dfn> tag is copied into these references.
The term contains subscripts, these are automatically copied into the reference.
This is a simple MathML equation.
{ "width" : 48,
"defaultUnused" : "Bogus",
"fields": [
{ "msb": 4,
"lsb": 0,
"name": "field 4:0",
"attr": "ro"
}, {
"msb": 7,
"lsb": 6,
"name": "Very long name that will never fit"
}, {
"msb": 9,
"name": "bit9"
}, {
"lsb": 10,
"name": "bit10",
"addClass": "svg_error"
}, {
"lsb": 11,
"name": "bit11"
}, {
"lsb": 12,
"name": "bit12",
"value": "1"
}, {
"lsb": 13,
"name": "bit13",
"href": "field-bit13"
}, {
"lsb": 14,
"msb": 24,
"name": "bit 20:14",
"value": "value"
}, {
"lsb": 25,
"msb": 32,
"name": "byte",
"value": [ "A", "B", "C", "D", "E", "F", "G", "H"]
} ] }
These are references to fields that were defined as terms in this JSON example.
| Bit Location | Register Description | Attributes | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 |
Z – This field is a very special field. This is the middle paragraph. This is the last paragraph. |
RO | |||||||||
| 2:1 |
bit1_2 – Bits 1 & 2 |
RW | |||||||||
| 3 | bit3 – three | RW | |||||||||
| 4 |
Ab – four |
RW | |||||||||
| 5 | bit5 – five | RW | |||||||||
| 6 |
bit 6a – six a bit 6b – six b bit 6c six c |
RW | |||||||||
| 7 | bit7 | RW | |||||||||
| 8 | bit8 - eight | RW | |||||||||
| 9 | bit9 | RW | |||||||||
| 14 |
bit 14a
fourth |
RW | |||||||||
| Bit Location | Register Description | Attributes |
|---|---|---|
| 3:0 |
Completion Timeout Ranges Supported – This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other Functions this field is Reserved and MUST be hardwired to 0000b. Four time value ranges are defined:
Bits are set according to the table below to show timeout value ranges supported.
All other values are Reserved. It is STRONGLY RECOMMENDED that the Completion Timeout mechanism not expire in less than 10 ms. |
HwInit |
| 4 |
Completion Timeout Disable Supported – A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is REQUIRED for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. This mechanism is OPTIONAL for Root Ports. For all other Functions this field is Reserved and MUST be hardwired to 0b. |
RO |
| 5 |
ARI Forwarding Supported – Applicable only to Switch Downstream Ports and Root Ports; MUST be 0b for other Function types. This bit MUST be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. See Section 6.13 for additional details. |
RO |
| 6 |
AtomicOp Routing Supported – Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; MUST be 0b for other Function types. This bit MUST be set to 1b if the Port supports this optional capability. See Section 6.15 for additional details. |
RO |
| 7 |
32-bit AtomicOp Completer Supported – Applicable to Functions with Memory Space BARs as well as all Root Ports; MUST be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit MUST be set to 1b if the Function supports this optional capability. See Section 6.15.3.1 for additional RC requirements. |
RO |
| 8 |
64-bit AtomicOp Completer Supported – Applicable to Functions with Memory Space BARs as well as all Root Ports; MUST be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit MUST be set to 1b if the Function supports this optional capability. See Section 6.15.3.1 for additional RC requirements. |
RO |
| 9 |
128-bit CAS Completer Supported – Applicable to Functions with Memory Space BARs as well as all Root Ports; MUST be 0b otherwise. This bit MUST be set to 1b if the Function supports this optional capability. See Section 6.15 for additional details. |
RO |
| 10 |
No RO-enabled PR-PR Passing – If this bit is Set, the routing element never carries out the passing permitted by Table 2-39 entry A2b that is associated with the Relaxed Ordering Attribute field being Set. This bit applies only for Switches and RCs that support peer-to-peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC MUST report the same value for this bit. Clearly this applies when both requests are forwarded. What about when only one of the requests is forwarded? For all other functions, this bit MUST be 0b |
HwInit |
| 11 |
LTR Mechanism Supported – A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports, Switches and Endpoints are PERMITTED to implement this capability. For a multi-Function device associated with an Upstream Port, each Function MUST report the same value for this bit. For Bridges and other Functions that do not implement this capability, this bit MUST be hardwired to 0b. |
RO |
| 13:12 |
TPH Completer Supported – Value indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions, this field is Reserved. Defined Encodings are:
See Section 6.17 for details. |
RO |
| 15:14 |
LN System CLS – Applicable only to Root Ports and RCRBs; MUST be 00b for all other Function types. This field indicates if the Root Port or RCRB supports LN protocol as an LN Completer, and if so, what cacheline size is in effect. Encodings are:
|
HWInit |
| 19:18 |
OBFF Supported – This field indicates if OBFF is supported and, if so, what signaling mechanism is used.
The value reported in this field MUST indicate support for WAKE# signaling only if:
Root Ports, Switch Ports, and Endpoints are PERMITTED to implement this capability. For a multi-Function device associated with an Upstream Port, each Function MUST report the same value for this field. For Bridges and Ports that do not implement this capability, this field MUST be hardwired to 00b. |
Hwinit |
| 20 |
Extended Fmt Field Supported – If Set, the Function supports the 3-bit definition of the Fmt field. If Clear, the Function supports a 2-bit definition of the Fmt field. See Section 2.2. MUST be Set for Functions that support End-End TLP Prefixes. All Functions in an Upstream Port MUST have the
same value for this bit. Each Downstream Port of a component
It is STRONGLY RECOMMENDED that Functions support the 3-bit definition of the Fmt field. |
RO |
| 21 |
End-End TLP Prefix Supported – Indicates whether End-End TLP Prefix support is offered by a Function. Values are:
All Ports of a Switch MUST have the same value for this bit. |
HwInit |
| 23:22 |
Max End-End TLP Prefixes – Indicates the maximum number of End-End TLP Prefixes supported by this Function. See Section 2.2.10.2 for important details. Values are:
If End-End TLP Prefix Supported is Clear, this field is RsvdP. Different Root Ports that have the End-End TLP Prefix Supported bit Set
For Switches where End-End TLP Prefix Supported is Set, this field MUST be 00b indicating support for up to four End-End TLP Prefixes. |
HwInit |
| 31 |
FRS Supported – When Set, indicates support for the optional Function Readiness Status (FRS) capability. MUST be Set for all Functions that support generation or receipt capabilities of FRS Messages. MUST NOT be Set by Switch Functions that do not generate FRS Messages on their own behalf. |
HwInit |
The No RO-enabled PR-PR Passing bit allows platforms to utilize PCI Express switching elements on the path between a requester and completer for requesters that could benefit from a slightly less 5 relaxed ordering model. An example is a device that cannot ensure that multiple overlapping posted writes to the same address are outstanding at the same time. The method by which such a device is enabled to utilize this mode is beyond the scope of this specification.
Something MUST happen.
Something MUST NOT happen.
Something SHOULD happen.
Something SHOULD NOT happen.
Something SHALL happen.
Something SHALL NOT happen.
Something is REQUIRED to happen.
Something is NOT REQUIRED to happen.
Something is RECOMMENDED to happen.
Something is NOT RECOMMENDED to happen.
Something is STRONGLY RECOMMENDED to happen.
Something is STRONGLY NOT RECOMMENDED to happen.
Something is OPTIONAL.
Something is INDEPENDENTLY OPTIONAL.
Something is PERMITTED to happen.
Something is NOT PERMITTED to happen.
This is a problem
This is a problem
Just a note
Body of the implementation note
Body of the implementation note
Advisement Text Body of the advisement
This is a paragraph with an inline issue.
This is a problem
This is a paragraph with an inline note.
Just a note
This is a paragraph with an inline impnote.
Just an impnote